Quadrature modulator with pulse-shaping

ABSTRACT

An IQ modulator and method for modulating a signal in accordance with I and Q symbols using derivative FIR&#39;s operating at the symbol rate and programmable multi-accumulators for waveform generator. 
     This provides advantages that reduced complexity is produced compared with traditional FIR&#39;s by a factor equal to the quotient of oversampling ratio and derivative order; programmability to Digital Very Low IF mode transmission is possible; the same circuit may perform interpolation for narrow band MA&#39;s; and reduced sets of coefficients enable implementation of two sets of coefficients for MA&#39;s, allowing fast handover between MA&#39;s such as EDGE and IS136.

FIELD OF THE INVENTION

This invention relates to IQ (In-phase component and Quadrature-phasecomponent) modulation of signals, and particularly though notexclusively to IQ modulation in wireless transmitters for communicationssystems such as cellular communications systems.

IQ modulators are commonly found in wireless transmitter applicationsproviding multimode modulations, i.e., modulations in a desired one ofmultiple modes such as EDGE (Enhanced Data-rates for GSM Evolution),IS136 (Second generation TDMA air interface standard), IDEN (IntegratedDigital Enhanced Network), ICO (Intermediate Circular Orbit), IS95 (CDMAair interface standard) and other schemes using linear modulation.

BACKGROUND OF THE INVENTION

In the field of this invention it is known that IQ modulation may beperformed by using finite impulse response filters (FIR's) operating atan oversampling ratio (of the sampling rate of the I and Q samples) withcoefficients equal in number to the product of the oversampling ratioand the span length times of the I and Q samples.

It is desirable to provide a low cost and programmable modulator tohandle particularly the following different operating modes (MA's):

-   -   EDGE in DCR (Direct Conversion Receiver) or DVLIF (Digital        Very-Low Intermediate Frequency) modes with high oversampling        clocks    -   IDEN and IS136 in interpolation modes with high oversampling        clocks    -   IS95 in DCR mode with high oversampling clocks

In order to meet the requirements of low cost and programmability, sucha modulator should have:

-   -   low integrated circuit (IC) gate count;    -   high oversampling ratio (e.g., greater than 4);    -   reduced sets of coefficients for software transmitter (TX)        handover between MA's without IC re-programming.    -   low power consumption

However, such combined requirements have been difficult to meet.

A need therefore exists for an IQ modulator and method wherein theabovementioned disadvantage(s) may be alleviated.

Prior Art

U.S. Pat. No. 6,031,431 (Sanjay) discloses a simplified IQ modulator andmethod. A Nyquist filter is used with an interpolator. This performsboth pulse shaping and interpolation functions.

European Patent Application EP-A-0881 764 (Commquest) describes a methodfor variable-rate down sampling. An anti aliasing filter matches thesampling rate and a frequency controlled oscillator ensues thatfrequency synthesis is maintained in the digital domain.

Statement of Invention

In accordance with the present invention there is provided an IQmodulator and method as claimed in claim 1 and claim 10 respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

One digital pulse-shaping multi-accumulator waveform generatorincorporating an IQ modulator according to the present invention willnow be described, by way of example only, with reference to theaccompanying drawings, in which:

FIG. 1 shows a block schematic diagram of a signal processing flow for aFIR for use in EDGE mode IQ modulation in the multi-accumulator waveformgenerator incorporating the present invention;

FIG. 2 shows a block schematic diagram of a multi-accumulator polynomialgenerator used in the multi-accumulator waveform generator;

FIG. 3 shows a block schematic diagram of a IF Phase Generator with I/QPhase Correction which may be used in the multi-accumulator waveformgenerator;

FIG. 4 shows a block schematic diagram of a Programmable Complex Pulseshaping Digital Modulator;

FIG. 5 shows a block schematic diagram of a complex FIR filter;

FIG. 6 shows a block schematic diagram of a particular serialimplementation of the FIR of FIG. 5;

FIG. 7 shows a block schematic diagram of a TX processing portion usingoversampled digital-to-analog converters using a pulse-shaping FIRfilter operating at a sampling frequency less than that of theoversampled digital to analog converter;

FIG. 8 shows a block schematic diagram of a further alternative TXprocessing portion of FIG. 7 with an interpolator added between thepulse-shaping filter and the oversampled digital-to-analog converter;and

FIG. 9 shows a block schematic diagram of TX processing portion where aderivative FIR operates at the symbol rate frequency and themulti-accumulator polynomial, generator operates directly at theoversampling clock rate of the oversampled digital-to-analog converter.

DESCRIPTION OF PREFERRED EMBODIMENTS

In a preferred IQ modulator for a low-cost re-programmable ICimplementation for portable cellular applications, a multi-accumulatorpolynomial generator is used. Use of the multi-accumulator polynomialgenerator allows any desired type of pulse-shaping filter to beachieved, the impulse response on each symbol period being approximatedby a 4^(th) order polynomial expression, where the coefficients of eachof the four orders is expressed as X1d(i), X2d(i), X3d(i) and X4d(i),where i is the corresponding symbol period index. Rather than havingfinite impulse response filters (FIR's) operating at the oversamplingratio, they operate at the symbol period 1X.

FIG. 1 shows the signal processing flow for producing the filtercoefficients for such a 4^(th) order FIR operating at the symbol period1X.

For example, in EDGE mode, the impulse response span over 5 symbolperiods, so only 5 taps per FIR are required, resulting in complexityequal to 5*270.8333*4=5410 kilo-operations per second (270.8333 ksym/sbeing the required EDGE symbol period); in North American DigitalCellular (NADC) mode, the impulse response spans over 9 symbol periods,so 9taps per FIR is required, resulting in complexity equal to9*24.3:*4=874.8 kilo-operations per second (24.3 ksym/s being therequired NADC symbol period).

More generally, it will be appreciated that the complexity for awaveform generator approach is equal to: Span*1X*Derivative Order, whereSpan is the number of symbols that the impulse response spans, andDerivative Order is the maximum derivative order chosen to approximatethe impulse response with a desired accuracy.

It should be noted that if a traditional FIR approach operating at theoversampling ratio were chosen, then a 5*16 tap FIR operating at 16X thesample period would be required for EDGE mode operation. Although someimplementations can reduce the number of taps to 5, the complexity ofsuch a traditional approach would still be 5.*16*270.8333=21667kilo-operations per seconds, i.e., still 4 times more complex than themulti-accumulator approach of the present example.

It will be appreciated that the complexity increases as the oversamplingratio increases. The oversampling clock (i.e., the output clock) isusually increased the due to the need to reduce the image frequencycomponents and to reduce the order of the analog reconstruction filtersafter the digital-to-analog converters and to the need to spread thequantization noise over a wider bandwidth to increase the outputsignal-to-noise ratio.

However, it will be understood that with the invention, the FIR's arenot required to operate at the output oversampling frequency, but at thesame frequency as the input rate (e.g., at the symbol rate when used forpulse-shaping operation, or at the input rate when used forinterpolation) while only the polynomial waveform generator based on amulti-accumulator structure that operates at the oversampling clockrate, allowing higher oversampling clock rates and allowing programmableoutput clocks without the need to change the FIR's coefficients orstructure. Thus, in the invention the oversampling clock can be madeprogrammable without the need to change any programming coefficients oradding complexity, it only requires changing the clock value.

In FIG. 1 is shown the signal processing flow arrangement 100 forproducing FIR coefficients with a 6 symbol span length and with a 4^(th)order Derivative (as required for EDGE mode operation withpre-distortion).

As can be seen, the signal processing flow arrangement 100 has fourgroups of multipliers 112, 122, 132 and 142, each of which receives arespective coefficient (X1d(0) to X4d(5)) and an appropriate I symbolvalue Iin(n) to Iin(n−4). It will be understood that FIG. 1 shows thesignal processing flow only for I symbol processing, and that a similarsignal processing flow occurs for Q symbol processing. The outputs ofthe multipliers are applied to summation nodes 114, 124, 134 and 144,which sum the respective multiplier outputs in each group to produce thefour order outputs x1d, x2d, x3d and x4d, which are applied to amulti-accumulator structure (as will be explained) which forms apolynomial waveform generator.

The operation can-therefore be described as follows:x1d(n)=Σ5i=0 X1d(i)·Iin(i)x2d(n)=Σ5i=0 X2d(i)·Iin(i)x3d(n)=Σ5i=0 X3d(i)·Iin(i)x4d(n)=Σ5i=0 X3d(i)·Iin(i)where n is the index at the symbol rate 1X (Pulse-Shaping mode) or atthe input rate FinX (Interpolation mode), and where X1d, X2d, X3d andX4d are the programmable coefficients of the first FIR, the second FIR,the third FIR and the fourth FIR respectively.

Referring now also to FIG. 2, the FIR coefficients produced in FIG. 1are applied to inputs of a polynomial waveform generator 200 operatingat the system oversampling ratio OVSX, which is chosen in the presentexample as OVSX=16 for EDGE mode operation. In the present example afourth order polynomial waveform generator is used.

As can be seen, the polynomial waveform generator 200 utilises theoutputs x1d, x2d, x3 and x4d (together with a further set of values x0d(which are a set of programmable fixed initial values that are loaded atthe start of the transmission to set an initial trajectory point and/orto compensate a DC offset value) with adders 212, 222, 232, 242,accumulator registers 214, 224, 234, 244 and shift registers 216, 226,236, 246 (to divide by a power of 2 by right-shifting by 2, 3 or 4 bitsas desired) to progressively accumulate the I (or Q) values which areoutput from the generator as signals Iout (or Qout).

The accumulators 244, 234, 224 load (at each symbol clock pulse at theclock rate finX) the values x3d, x2d, x1d and then accumulate (at eachclock pulse at the clock rate fovs) in order to calculate the firstorder derivative, while the last accumulator 214 is continuouslyaccumulating without re-initialization of its value except at thebeginning of the transmission burst.

The word output Iout (or Qout) can be expressed as, (assuming adivide-by-OVSD happening in the shift registers 246, 236, 226, 216section, and an OVSX oversampling ratio=fovs/f1x):

$\begin{matrix}{{{Iout}\mspace{11mu}\left( {n,k} \right)} = {{{Iout}\mspace{11mu}\left( {{n - 1},{OVSX}} \right)} + {{k.{x1d}}\;{(n)/{OVSD}}} + {k\;{\left( {k - 1} \right)/{{2!}.{x2d}}}\;{(n)/{OVSD2}}} + {k\;\left( {k - 1} \right)\;{\left( {k - 2} \right)/{{3!}.{x3d}}}\;{(n)/{OVSD3}}} + {k\;\left( {k - 1} \right)\;\left( {k - 2} \right)\;{\left( {k - 3} \right)/{{4!}.{x4d}}}\;{(n)/{OVSD}^{4}}}}} & (1)\end{matrix}$Where n is the index at the symbol rate and k is the index at theoversampling rate OVSX (i.e., k=[0:OVSX−1])

Iout(0,0)=x0=initial value at the modulation start burst. x0 can includealso a DC offset correction value for LO leakage reduction. For the Ipath x0=I_DCoffset and for the Q path x0=Q_DCoffset, these values beingprogrammed by a host processor (not shown).

By replacing each term x1d, x2d, x3d and x4d for the fourth ordersystem, the word output Iout (or Qout) can be re-expressed as:

$\begin{matrix}{{{Iout}\;\left( {n,k} \right)} = {{{{Iout}\;\left( {{n - 1},{OVSX}} \right)} + {\sum{5i}}} = {0\mspace{11mu}{Iin}\;{(i).\left\lbrack {{{k.{X1d}}\;{(i)/{OVSD}}} + {{{k\left( {k + 1} \right)}/{{2!}.{{X2d}(i)}}}/{OVSD2}} + {k\;\left( {k - 1} \right)\;{\left( {k - 2} \right)/{3!}}{.3}d\;{(i)/{OVSD3}}} + {k\;\left( {k - 1} \right)\;\left( {k - 2} \right)\;{\left( {k - 3} \right)/{{4!}.{X4d}}}\;{(i)/{OVSD4}}}} \right\rbrack}}}} & (2)\end{matrix}$

By rewriting the equation (2) for n,n−1,n−2, . . . , then Iout can beexpressed as function of Iin:

Iout (n, k) = Iin(n).h5(k) + Iin(n − 1).h4(k) + Iin(n − 2).h3(k) + Iin (n − 3).h2(k) + Iin(n − 4).h1(k) + Iin(n − 5).h0(k) + Iin(n − 6).h − 1 + Iin(n − 7).h − 1 + … .where:h5 = (k)[k(k − 1)(k − 2)(k − 3)/4!.X4d(5)/OVSD⁴ + k(k − 1).(k − 2)/3!.X3d(5)/OVSD³ + k(k − 1)/2.X2d(5)/OVSD² + k.X1d(5)/OVSD]h4(k) = [k(k − 1)(k − 2)(k − 3)/4!.X4d(4)/OVSD⁴ + k(k − 1).(k − 2)/3!.X3d(4)/OVSD³ + k(k − 1)/2.X2d(4)/OVSD² + k.X1d(4)/OVSD + h5(OVSX)]h3(k) = [k(k − 1)(k − 2)(k − 3)/4!.X4d(3)/OVSD⁴ + k(k − 1).(k − 2)/3!.X3d(3)/OVSD³ + k(k − 1)/2.X2d(3)/OVSD² + k.X1d(3)/OVSD + h4(OVSX)]h2(k) = [k(k − 1)(k − 2)(k − 3)/4!.X4d(2)/OVSD⁴ + k(k − 1).(k − 2)/3!.X3d(2)/OVSD³ + k(k − 1)/2.X2d(2)/OVSD² + k.X1d(2)/OVSD + h3(OVSX)]h1(k) = [k(k − 1)(k − 2)(k − 3)/4!.X4d(1)/OVSD⁴ + k(k − 1).(k − 2)/3!.X3d(1)/OVSD³ + k(k − 1)/2.X2d(1)/OVSD² + k.X1d(1)/OVSD + h2(OVSX)]h0(k) = [k(k − 1)(k − 2)(k − 3)/4!.X4d(0)/OVSD⁴ + k(k − 1).(k − 2)/3!.X3d(0)/OVSD³ + k(k − 1)/2.X2d(0)/OVSD² + k.X1d(0)/OVSD + h1(OVSX))andh − 1 = OVSX.(OVSX − 1).(OVSX − 2).(OVSX − 3)/4!.(∑5i = 0X4d(i)/OVSD⁴) + (OVSX.(OVSX − 1).(OVSX − 2)/3!.(∑5i = 0X3d(i)/OVSD³) + OVSX.(OVSX − 1)/2!.(∑5i = 0X2d(i)/OVSD²) + OVSX.(∑5i = 0X1d(i)/OVSD)

If Iout is expressed as a function of the required impulse responseimp(t)(at oversampling ratio OVSX) to provide both modulation andpre-distorsion:

Iout(n, k) = Iin(n).imp(k) + Iin(n − 1).imp(k + OVSX) + Iin(n − 2).imp(k + 2 * OVSX) + Iin(n − 3).imp(k + 3 * OVSX) + Iin(n − 4).imp(k + 4 * OVSX) + Iin(n − 5).imp(k + 5 * OVSX)  if  Iin  is  considered  oversampled  at  OVSX  with  zeros  filling  between  1X  samples.

From this the following are obtained:h5(k)=imp(k)h4(k)=imp(k+OVSX)h3(k)=imp(k+2*OVSX)h2(k)=imp(k+3*OVSX)h1(k)=imp(k+4*OVSX)h0(k)=imp(k+5*OVSX)  (3)

By solving above equations (3), the coefficients X1d, X2d, X3d, X4d areextracted to match the impulse response.

Comparative measurements between IQ modulators utilizing the aboveapproach and IQ modulators using the traditional prior art approach haveshown significant similarity between the results of the two approaches.

It may be noted that since OVSX is chosen to be a power of 2 number, thedivision inside the waveform generator OVSD is performed by shiftingright the bits depending on the chosen value OVSX.

It is also possible to do a non-power of 2 interpolation factor wherethe oversampling clock fovs is any integer number multiplier relative tothe input rate finX (i.e., fovsX=FinX*OVSX), while the 246, 236, 226 and216 values OVSD are shift right operations.

Also, it is possible to program different coefficients between the I andQ path in order to provide Image Rejection Enhancement for Direct Launchsystems where greater sensitivity to I/Q gain and phase mismatch isobserved at 2 GHz or above.

Also, it is possible to pre-distort the impulse response so as tocompensate the subsequent analog reconstruction filters (not shown) andso as to enable a better compromise between noise output and EVM due tothe selected bandwidth, i.e., lower bandwidth will lower the noise levelbut will increase EVM due to an increase of group and amplitude ripple.

In the case of EDGE mode operation as an example, the serial data are at3x times the symbol rate. A phase mapping ‘3Π/8 O8PSK’ is performedwhich gives 16 different phase values, commonly called “phasemod”.

A Low IF mode can be selected through the software programming interface(SPI) by adding to the phasemod a linear phase increment depending onthe IF value selected by a SPI programming bit. As shown in FIG. 3, theIF linear phase increment is implemented using accumulators 310 and 320operating at 1X, having as inputs I and Q phase corrections that areprogrammed through SPI bits Iphaseadjust and Qphaseadjust.

The output phase(s) of the IF phase generator(s) are added to the phasemapping output phasemod to address a ROM table (not shown) to generatethe cosine and sine terms on complement of 2 10-bit words, TM_I andTM_Q, at the programmed input frequency (fin) rate (normally 1X).

In Low IF mode, the I and Q outputs TM_I and TM_Q are frequency shiftedby the programmed IF value, requiring then that the pulsing shapingfilter be also shifted in frequency, to avoid low pass filtering themodulation that is now IF centered. To do that, a complex FIR pulseshaping is required (i.e., using complex values and replacing the realcoefficients by complex coefficients, i.e.,X1dIc=X1dIr+j.X1dIiX2dIc=X2dIr+j.X2dIiX3dIc=X3dIr+j.X3dIiX4dIc=X4dIr+j.X4dIiandX1dQc=X1dQr+j.X1dQiX2dQc=X2dQr+j.X2dQiX3dQc=X3dQr+j.X3dQiX4dQc=X4dQr+j.X4dQi

The FIR 1X filter referred to above thus becomes a complex FIR filter,as shown in the overall block diagram of the programmable pulse-shapingcomplex digital IQ modulator 400 of FIG. 4.

The complex FIR 410 that operates at an input frequency (fin) which isnormally at 1X (i.e., at the symbol rate) is based on a real andimaginary FIR's (510 and 520 respectively), as shown in FIG. 5.

It may be noted that in IF=0 mode, the imaginary coefficients will beprogrammed to 0, such that real pulse shaping only is performed.

The implementation of the FIR at 1X could be optimized in die area byreplacing the n multipliers operating at 1X by a single multiplieroperating at n*1X, i.e., a change from parallel to serial FIRimplementation. The choice of whether to implement this optimization isleft to the discretion of the designer, based on the IC process speedand density.

Also, it is possible to replace the multiplier at 1X rate or n*1X rateby a ROM table (not shown) that is addressed by input Iin or Qin, if noprogrammability is required for the coefficients.

It will be understood that a ROM table in a traditional approach wouldincrease in size versus the oversampling clock and would be required tochange versus programming the oversampling clock, while in the case ofthe present invention the ROM table does not change (either it size orit contents) with the oversampling clock (since it operates at symbolrate data).

FIG. 6 shows an example of a serial (shared, multiplexed) FIRimplementation 600 of 6 taps*4 FIR*1X rate which may be used analternative to the multiple (parallel) multiplier arrangement describedabove.

Complex pulse shaping at 1X rate allows a Low IF mode for lower EVM byhaving the image shifted at Low IF and reducing LO leakage effect on EVMand having a loop injection LO (if present) non-harmonically related tothe main TX frequency for additional reduction of LO re-modulation.

Also, complex pulse-shaping can pre-distort any TX IF filter group delayand amplitude for additional EVM improvement.

For EDGE for example, the reconstruction filter has some effect on theEVM of the modulation.

The impulse response could be pre-distorted for a given bandwidthsetting (where no radio phasing is required). A span of 6 symbols isenough for the pre-distortion since the bandwidth of such reconstructionfilters are in the range of 400–600 KHz.

It will be appreciated that, due to the presence of themulti-accumulator waveform generator, it is possible to re-use thisblock as an interpolator of 4th order. Since NADC mode operationrequires a span over 9 symbols, rather than having to generate 9coefficients per filter at 1X the interpolation mode as described belowcould be used.

In bypass mode, rather than transferring one bit serial data on TSDTX,pulse-shaped I/Q data are sent over the SSI (the modulation beingperformed in software) for narrow band systems. The I/Q data arrive at arate FinX that can be programmed through a host processor. As anexample, NADC I/Q data at a rate of 16X (388 kilo-data per second), andan interpolation factor of 8, results on interpolated I/Q data's of3.1104 Mhz at the DAC input.

In the interpolation mode, the coefficients of the FIR's are programmedsuch that the waveform generator output fits the input at FinX and itsvarious derivatives calculated at FinX.

Referring now also to FIG. 7, some digital-to-analog converters (such asthe D-to-A implementation 700) have an oversampled structure calledDelta-Sigma D/A's where the oversampling clock fovs2 is usually 40 to100 times the input symbol clock. If prior art pulse shaping filter wereused, the FIR multipliers would be limited in speed to fovs1 so theoutput word Iout1 (or Qout1) will only be oversampled at fovs1 and theirassociated digital quantization noise is spread only at +/−fovs1/2.

Another possible TX processing arrangement inserts interpolation stagesbetween the pulse-shaping FIR and the Delta-Sigma Modulators as shown inFIG. 8. Such a structure as the arrangement 800 suffers however frommodulation accuracy (EVM) for some MA's like EDGE, due to the nature ofthe interpolation structure, mainly when the interpolation factor ishigh (i.e., fovs2/fovs1).

Referring now to FIG. 9, to improve on the disadvantageous arrangementsof FIG. 7 and FIG. 8, the present invention may make use of the IQwaveform generator processing arrangement 900, based on the above IQwaveform generator replacing the pulse-shaping FIR by first-order,second-order, etc. derivative FIR's operating at the symbol rate clockand feeding a multi-accumulators waveform generator, where themulti-accumulator waveform generator operates directly at a higher clockrate, and particularly at fovs2, similar to the Delta-Sigma Modulatorsclock rates, since the accumulators can operate at higher clock speeds,thus allowing the quantization noise to spread directly over +−fovs2/2and without the need to increase complexity since the FIR's operate atthe symbol rate clock. In this way, the multi-accumulator waveformgenerator can be used to generate oversampling I and Q directly, with anoversampling clock as high as, say, 50 to 100 times the symbol rate.

It will be appreciated that the oversample clock can be directlyconnected to the Delta-Sigma oversampling clock, avoiding any currentdrain or area size increase since no multipliers are required to operateand no loss in the modulation accuracy occurs. It will be understoodthat such use of the same ovesampling rate serves to spread quantisationnoise and lower the noise floor.

It will be appreciated that the Complexity of the Multi-accumulatorWaveform Generator is summarized as:C _(—) WG=Span*Derivative Order*1X in multiply/add operations

The Complexity of the traditional FIR using the fact that the input isconstant over a symbol is:C _(—) TFIR=Span*Oversampling*1X in multiply/add operations

Thus, it will be understood that both approaches have the samecomplexity when the oversampling ratio is equal to the derivative order.

However, for a system like EDGE which requires Low EVM, an oversamplingof 16 is required. A 4^(th) order derivative meets both the EVM andSpectral Mask, and so a ratio of ¼ of the complexity exists when usingthe multi-accumulator waveform generator approach described above.

Also, when oversampled digital-to-analog converters are used withoversampling clock higher than 40 times the symbol rate, the use of themulti-accumulator waveform generator reduces the complexitysignificantly.

The following table shows the Complexity of the Waveform Generator forvarious MA's:

Over- 1x C WG Software Symbol Derivative sampling (symbol) Multiply/ LowModulation & Span Order Ratio (MHz) Add/Subtract IF InterpolationGSM/EDGE 6 4 16 0.270833 6.5000 Yes No NADC 9 4 16 0.0243 0.8748 No YesWBCDMA 16 4 8 3.84 245.7600 No No BLUETOOTH 2 4 16 1 8.0000 No No

It will be understood that the IQ modulator and method described aboveprovides the following advantages:

-   -   Reduced complexity versus traditional FIR's by a factor equal to        the oversampling ratio divided by the derivative order.    -   Programmability to Digital Very Low IF mode TX.    -   The same circuit can perform interpolation for narrow band MA's.    -   Reduced sets of coefficients enables implementation of two sets        of coefficients allowing for fast handover between MA's, e.g.,        between EDGE and IS136.

1. An IQ modulator for modulating in-phase (‘I’) and quadrature-phase(‘Q’) components of an input signal in accordance with I and Q symbols,comprising: I and Q FIR means for filtering the I and Q signalcomponents, respectively, and generating I and Q sets of FIR components(x1d–x4d) corresponding to said I and Q input signal componentsmultiplied by sets of coefficients, said FIR means operating at thesymbol rate; and a polynomial waveform generator comprising I and Qaccumulator means, said I and Q accumulator means comprising I and Qsets of first accumulator elements and I and Q second accumulatorelements, said I and Q sets of first accumulator elements being arrangedto load said I and Q FIR signal components at the symbol rate andaccumulate at an over-sampling rate so as to calculate first orderderivatives, and said I and Q second accumulator elements being arrangedto accumulate progressively, without reinitialization except at abeginning of a transmission burst, the outputs of said I and Q sets offirst accumulator elements and produce therefrom I and Q signalcomponents modulated with the I and Q symbols.
 2. The IQ modulatoraccording to claim 1 wherein the I and Q accumulator means has aprogrammable over-sampling ratio.
 3. The IQ modulator according to claim1 wherein the I and Q FIR means comprises multiplier means for producinga plurality of FIR filter coefficients.
 4. The IQ modulator according toclaim 3 wherein the I and Q FIR means comprises a plurality ofmultiplier arrangements for respectively producing pluralities of FIRfilter coefficients.
 5. The IQ modulator according to claim 3 whereinthe FIR means comprises a serial multiplexed multiplier arrangement forproducing the plurality of FIR filter coefficients.
 6. The IQ modulatoraccording to claim 3 wherein the FIR means comprises look-up table meansfor looking up from predetermined values in a look-up table values forproducing the plurality of FIR filter coefficients.
 7. The IQ modulatoraccording to claim 1 further comprising digital-to-analog convertermeans for operating at an over-sampling rate, coupled directly after themulti-accumulator means.
 8. A method of modulating in-phase (‘I’) andquadrature-phase (‘Q’) components of an input a signal in accordancewith I and Q symbols, the method comprising: providing I and Q FIRmeans, filtering the I and Q signal components respectively andgenerating I and Q sets of FIR components corresponding to said I and Qinput signal components multiplied by sets of coefficients, said FIRmeans operating at the symbol rate; and providing I and Q accumulatormeans, said I and Q accumulator means comprising I and Q sets of firstaccumulator elements and I and Q second accumulator elements, said I andQ sets of first accumulator elements loading said I and Q FIR signalcomponents at the symbol rate and accumulating at an over-sampling rateso as to calculate first order derivatives, and said I and Q secondaccumulator elements being arranged to accumulate progressively, withoutre-initialization except at a beginning of a transmission burst, theoutputs of said I and Q sets of first accumulator elements and producingtherefrom the I and Q signal components modulated with the I and Qsymbols.
 9. The method according to claim 8 wherein themulti-accumulator means has a programmable oversampling ratio.
 10. Themethod according to claim 8 wherein the I and Q FIR means comprisesmultiplier means for producing a plurality of FIR filter coefficients.11. The method according to claim 10 wherein the FIR means comprises aplurality of multiplier arrangements for producing respectivepluralities of FIR filter coefficients.
 12. The method according toclaim 10 wherein the FIR means comprises a serial multiplexed multiplierarrangement for producing the plurality of FIR filter coefficients. 13.The method according to claim 10 wherein the FIR means comprises look-uptable means for looking up from predetermined values in a look-up tablevalues for producing the plurality of FIR filter coefficients.
 14. Themethod according to claim 8 further comprising providingdigital-to-analog converter means operating at an over-sampling rate,coupled directly after the multi-accumulator means.
 15. The IQ modulatoraccording to claim 1 wherein said I FIR means of the I and Q FIR meanscomprises complex I FIR filter means including real and imaginary I FIRmeans, and said Q FIR means of the I and Q FIR means comprises complex QFIR filter means including real and imaginary Q FIR means.
 16. Themethod according to claim 8 wherein said I FIR means of the I and Q FIRmeans comprises complex I FIR filter means including real and imaginaryI FIR means, and said Q FIR means of the I and Q FIR means comprisescomplex Q FIR filter means including real and imaginary Q FIR means.